A flash memory system implemented as a Multi-Level Cell (MLC) flash memory is provided for storing more than one bit of data on each memory cell. The writing of data into an MLC flash memory is typically slower than the writing of data into a Single-Level Cell (SLC) flash memory that stores only one bit of data per cell. Therefore, a storage system based on an MLC flash memory might not be capable of recording a stream of incoming data transmitted to it at a higher writing rate.
Typically in cases where data is produced at a rate too high to be directly stored, a cache memory mechanism is provided and designed to operate fast enough to handle the incoming data stream. The cache memory utilizing a second (and faster) memory is implemented between the input data source and the main (and slower) memory. The input data stream is first written into the faster cache memory, and at a later stage is copied from this faster cache memory into the main memory. As the copying operation is typically performed in the background, it does not have to meet the strict performance conditions imposed by the input data stream rate, and therefore the lower write performance of the main memory is no longer an obstacle.
However, the implementation of a second memory for caching has its drawbacks. Such implementation requires additional components for the cache memory and its control, and it complicates the design and management of the memory system.
The prior art include U.S. Pat. No. 5,930,167 to Lee et al., which discloses a memory method and system for caching write operations in a flash memory storage system while achieving the benefits of caching in MLC flash memories but with less of the disadvantages. The MLC flash memory media is configured to operate as its own cache memory. This is possible since memory cells that store multiple bits can be further implemented to operate similar to SLC memory cells and store only a single bit each, which is an easier task from a technological point of view. As a result, the MLC memory cells can be implemented to achieve the faster write performance characterizing the SLC flash memory. The Lee Patent is incorporated by reference for all purposes as if fully set forth herein.
Known in the art techniques, such as that of Lee et al., provide a “built-in” faster cache memory embedded within the MLC flash memory storage system. When data bits are received for storage, they are first written into memory cells that are set to operate in SLC mode. This first writing operation can be done relatively fast. Following this operation, in the background and when time permits it, the data bits are copied from the SLC cells into memory cells that are set to operate in MLC mode. Thus, as the system is designed to employ the higher storage density of the MLC flash memory storage system, it further handles the faster input stream than could not be handled without the cache memory mechanism.
There are two possible methods for configuring a flash memory system while utilizing such an SLC caching scheme:                A. A dedicated cache—a specific portion of the memory cells is always allocated to operate in SLC mode, while other cells are allocated to operate in MLC mode only. In other words, while memory cells operating in SLC mode (SLC cells) and memory cells operating in MLC mode (MLC cells) co-exist within the storage system at the same time, each specific memory cell is either allocated to operate in SLC mode or in MLC mode, and cannot be alternately allocated to operate in SLC mode at one point in time and in MLC mode at another point in time.        B. A mixed cache—at least some of the memory cells change modes during the system's operation. That is—a specific memory cell may be allocated to operate in SLC mode at one point in time and utilized for caching data, while at a second point in time the same memory cell may be allocated to operate in MLC mode and utilized for high density data storage in the main memory.        
The dedicated cache method is much simpler to manage in flash memory systems than the mixed cache method. Each portion of the memory cells is pre-allocated to operate either in SLC mode or in MLC mode. Therefore, no real-time mode switching is required. Furthermore, there is no need to provide an information management module for storing and detecting the current operation mode of any memory portion.
But even though this advantage is clear, the Lee patent discloses a storing system that applies the more complex mixed cache method, per column 2 line 49:                “Nor is it necessary to dedicate some portion of the flash EEPROM memory to operate only as a write cache . . . . Therefore, portions of the flash EEPROM memory of the present invention that store data with the high density can also be operated as a write cache . . . . The identity of the memory sectors being used for long term, high density storage are maintained, such as by a file allocation table, in order to be able to direct low density incoming data to sectors that are unused.”        
An explanation for utilizing the more complex mixed cache method is further given in the Lee patent, per column 2 line 51:                “Use of a dedicated portion of the memory as a write buffer would cause the cells within that portion to be used much more than other portions of the memory, contrary to the usual desire to evenly wear the memory.”        
In other words, because each chunk of incoming data is written twice, once in SLC mode (when being cached) and once in MLC mode (when copied to main memory), and since typically the portion of memory cells allocated to the cache memory is much smaller than the portion allocated to the main memory, then over time on average a memory cell allocated only to the cache memory is written and then erased more frequently than a memory cell allocated only to the main memory.
Flash memory cells are known to wear out during use, i.e. the more write/erase cycles they go through, the more wear they suffer. Therefore, according to Lee, memory cells allocated to the cache according to the dedicated cache method, will wear out much faster than the other memory cells, and might reach the end of their lifetime (i.e. the end of their useful functional capability) while the cells not used for the cache are still functioning well.
Therefore, the Lee patent applies the mixed cache method in order to evenly distribute the wear out over all of the memory cells, as no cell is constantly heavily used in the cache.
Actually, the Lee patent could strengthen its argument against utilizing the dedicated method even further, per column 3 line 2:                “ . . . because instances of low density programming can cause more wear than instances of high density programming.”        
Therefore, not only are the memory cells of the cache memory written more frequently and so tend to wear out more quickly, but also, according to the Lee patent, even under equal number of write/erase cycles—a memory cell configured to operate in SLC mode is worn out earlier than a memory cell configured to operate in MLC mode.
The Lee patent further mentions that there is one case in which the dedicated cache method may be applied, per column 9 line 44:                “Alternatively, in applications where the use of the memory system is not expected to be large enough to require such wear leveling, certain blocks or sectors may be dedicated for the initial two-state data writes.”        
In other words, if the storage system is written to so infrequently that even without the employing of wear leveling techniques no memory cell is expected to be worn out, then there is place to apply the dedicated cache method.
Techniques for achieving wear leveling in order to evenly distribute the wear out over all of the memory blocks are well known in the art. They include U.S. Pat. No. 6,230,233 to Lofgren et al., U.S. Pat. No. 5,341,339 to Wells, U.S. Pat. No. 5,568,423 to Jou et al., U.S. Pat. No. 5,388,083 to Assar et al., U.S. Pat. Nos. 5,712,819, 6,570,790, and 5,963,480 to Harari, and U.S. Pat. No. 6,831,865 to Chang et al. All of those patents are incorporated by reference for all purposes as if fully set forth herein.
All of the above prior art approaches are based on counting the number of write/erase cycles each block of flash memory cells goes through, and using these counts for deciding on which block to allocate when a new block is needed for writing. Indeed, Lee also uses this approach, going the further step of keeping separate SLC counts and MLC counts for each block.
To summarize, according to the Lee patent—the designer of such a self-cached MLC/SLC flash memory system can select only between the following alternatives:                A. Use the mixed cache method, employ wear leveling techniques, and get a storage system that can stand frequent writing. This is the main and recommended approach.        B. Use the dedicated cache method, do not employ wear leveling techniques, and get a storage system that may be used only where writing of data is infrequent.        
However, the main drawback of this approach is that the mixed cache method is much more complex to accomplish and handle, since a real-time mode switching management is required.
Therefore, it is desirable to provide a storage system employing a dedicated cache method, while overcoming the wear-out problems caused from frequently writing to the memory cells.